This invention relates to a semiconductor device, and more particularly to a semiconductor device using a tunnel effect element.
The size of MOSFETs is reduced based on the scaling rule in order to enhance the operation speed. However, in a submicron region, the scaling rule cannot be successfully applied. Particularly, in a region of 0.1 .mu.m or less, there occurs a problem that a desired switching operation of a transistor cannot be attained because of the short channel effect.
In order to cope with the above problem, an element which can maintain the transistor operation even when the channel length is reduced is proposed (W Honlein et al., "Influence of the MOS surface channel on a channel-to-contact diode characteristics", INFOS'79, Inst. Phys. Conf. Ser. No.50, Chapter 2, p. 133 1980). The element is obtained by applying a tunnel diode to the MOS structure and is referred to as a surface tunnel effect element with gate electrode in this specification.
The structure of the tunnel effect element is obtained by setting the conductivity types of the source diffusion layer and drain diffusion layer of a normal MOS transistor opposite to each other and enhance the impurity concentrations of the respective diffusion layers. For example, in this element, a gate insulating film of silicon oxide film is formed on the surface of a p-type silicon substrate and a gate electrode of Al or the like is formed on the gate insulating film (MOS structure). Then, an n.sup.+ -type source region and a p.sup.+ -type drain region are formed on both sides of the gate electrode.
The element can effect the transistor operation by controlling a voltage applied to the gate electrode as will be described below. For example, if a positive voltage (Vg&gt;0) is applied to the gate electrode, carriers are induced in a portion of the surface area of the silicon substrate which lies directly below the gate electrode so as to form an n.sup.+ -type channel region. As a result, a pn junction (tunnel diode) is formed of the n.sup.+ -type channel region and the p.sup.+ -type drain region.
In the above tunnel diode, when the drain voltage (Vd) is increased in a forward direction, a drain current (Id) increases along an "N"-shaped curve and an Id-Vd characteristic shown in FIG. 1 can be obtained. In the range to the peak point in FIG. 1, the forward current increases due to the tunnel effect, in a range from the peak point to the valley point, the current decreases since the amount of carriers which can tunnel through is reduced. The above Id-Vd characteristic is called a negative resistance characteristic. After the valley point, a diffusion current flows and the current increases.
In the tunnel effect element, the channel region can be controlled only by controlling the gate voltage. Since the depletion layer extends only in a portion near the source region, the punchthrough phenomenon which occurs in the conventional MOS transistor can be substantially eliminated and the element can be treated as an element suitable for miniaturization.
Since the tunnel effect element utilizes a tunnel current having no time delay, the element can be expected to be used as a high-speed element. Further, since the operation voltage of the drain is as low as 1V or less, the element can be practically used as a low-power-consumption element.
In the manufacturing operation, it is necessary to separately effect the ion-implantation processes for implanting ions into the source and drain regions so as to form the p- and n-type regions, but except this process, the element can be manufactured according to the conventional manufacturing process of MOS transistors.
An SRAM for statically storing a storage signal is widely used as one semiconductor memory device. As an SRAM cell, a cell formed of six MOS transistors and a cell formed of four MOS transistors and two high-resistance resistors are known. In either case, it is necessary to use six elements so as to form the SRAM cell.
An SRAM cell which is formed of three elements (two tunnel diodes and one MOS transistor) and effective for high integration is proposed (Jpn. Pat. Appln. KOKAI Publication No.58-153295). FIG. 2 shows the equivalent circuit of such an SRAM cell.
The SRAM cell is constructed by two tunnel (ESAKI) diodes ED1, ED2 series-connected in the forward direction between a high-level voltage source Vdd and a low-level voltage source Vss and a MOS transistor Tr in which one of the source and drain is connected to a connection node N of the tunnel diodes ED1 and ED2, the other one of the source and drain is connected to a bit line BL and the gate is connected to a word line WL.
FIG. 3 shows the current-voltage characteristics of the tunnel diodes ED1, ED2 of the above SRAM. The potential state becomes stable at the intersections A.sub.0, A.sub.1 between the characteristic curves of the tunnel diodes ED1, ED2 and exhibits latch characteristics. The SRAM utilizes the two stable states for dealing with storage signals.
The operation of writing and reading out a storage signal and the operation of holding (standby) the signal charge are effected by use of the MOS transistor Tr. That is, in the case of writing, the MOS transistor is set into the ON state to electrically connect a selected bit line and the connection node to each other. As a result, charges of an amount corresponding to the product of the parasitic capacitance of the connection node N and the voltage of the bit line BL are stored on the connection node N as a storage signal. The voltage of the bit line BL is selected to set the system to the stable state corresponding to the intersection A.sub.0 or A.sub.1.
In the case of reading, the MOS transistor is set into the ON state to read the charge stored on the connection node N as the storage signal via a selected bit line BL. In the case of standby, the MOS transistor is kept in the OFF state.
However, the SRAM has the following problem. That is, since a drive current (tunnel current) I.sub.0 of constant level always flows in the above SRAM, it is difficult to simultaneously improve the power consumption at the time of standby and the readout speed of the storage signal. This is because it is necessary to reduce the drive current I.sub.0 in order to suppress the power consumption at the time of standby and it is necessary to increase the drive current I.sub.0 in order to enhance the readout speed.
As described above, the conventional SRAM using tunnel diodes is a memory cell excellent in the high integration but has a problem that it is difficult to simultaneously attain the low power consumption and the high readout speed.